PRELIMINARY SPECIFICATIONS --- PROGRAMMED DATA PROCESSOR MODEL THREE (PDP-3) --- October, 1960 Digital Equipment Corporation Maynard, Massachusetts TABLE OF CONTENTS INTRODUCTION 1 General Description 1 System Block Diagram 1 Electrical Description 4 Mechanical Description 4 Environmental Requirements 5 CENTRAL PROCESSOR 6 Operating Speeds 6 Instruction Format 6 Number System 7 Indexing 8 Indirect Addressing 8 Instruction List 9 Manual Controls 20 STORAGE 22 STANDARD INPUT-OUTPUT 23 Paper Tape Reader 23 Paper Tape Punch 24 Typewriter 24 OPTIONAL INPUT-OUTPUT 26 Sequence Break System 26 High Speed In-Out Channel 26 Magnetic Tape 27 CRT Display 33 Real Time Clock 33 Line Printer 34 UTILITY PROGRAMS 35 FRAP System 35 DECAL System 35 Floating Point Subroutines 36 Maintenance Routines 37 Miscellaneous Routines 37 INTRODUCTION GENERAL DESCRIPTION The DEC Programmed Data Processor Model Three (PDP-3) is a highperformance, large scale digital computer featuring reliability inoperation together with economy in initial cost, maintenance and use. This combination is achieved by the use of very fast, reliable, solidstate circuits coupled with system design restraint. The simplicity ofthe system design excludes many marginal or superfluous features andthus their attendant cost and maintenance problems. The average internal instruction execution rate is about 100, 000operations per second with a peak rate of 200, 000 operations per second. This speed, together with its economy and reliability, recommends PDP-3as an excellent instrument for complex real time control applicationsand as the center of a modern computing facility. PDP-3 is a stored program, general purpose digital computer. It is asingle address, single instruction machine operating in parallel on 36bit numbers. It features multiple step indirect addressing and indexingof addresses. The main memory makes 511 registers available as indexregisters. The main storage is coincident current magnetic core modules of 4096words each. The computer has a built-in facility to address 8 modulesand can be expanded to drive 64 modules. The memory has a cycle time offive microseconds. SYSTEM BLOCK DIAGRAM The flow of information between the various registers of PDP-3 is shownin the System Block Diagram (Fig. 1). There are four registers of 36 bitlength. Their functions are described below. Memory Buffer The Memory Buffer is the central switching register. The word comingfrom or going to memory is retained in this register. In arithmeticoperations it holds the addend, subtrahend, multiplicand, or divisor. The left 6 bits of this register communicate with the InstructionRegister. The address portion of the Memory Buffer Register communicateswith the Index Adder, the Memory Address Register, and the ProgramCounter. In certain instructions, the address portion of the controlword does not refer to memory but specifies variations of aninstruction, thus, the address portion of the Memory Buffer is connectedto the Control Element. Accumulator The Accumulator is the main register of the Arithmetic Element. Sums anddifferences are formed in the Accumulator. At the completion ofmultiplication it holds the high order digits of the product. Indivision it initially contains the high order digits of the dividend andis left with the remainder. The logical functions AND, inclusive OR, and exclusive OR, are formed inthe Accumulator. Carry Storage Register The Carry Storage Register facilitates high-speed multiply and isproperly part of the Accumulator. In-Out Register The In-Out Register is the main path of communication with externalequipment. It is also part of the Arithmetic Element. In multiplicationit ends with the low order digits of the product. In division it startswith the low order parts of the dividend and ends with the quotient. The In-Out Register has a full set of shifting properties, (arithmeticand logical). * * * * * There are three registers of 15 bit length which deal exclusively withaddresses. The design allows for expansion to 18 bits. These registersare: Memory Addressing The Memory Address Register holds the number of the memory location thatis currently being interrogated. It receives this number from theProgram Counter, the Index Adder or the Memory Buffer. Program Counter The Program Counter holds the memory location of the next instruction tobe executed. Index Adder The Index Adder is a 15 bit ring accumulator. The sum of an instructionbase address, Y, and the contents of an index register, C(x), are formedin this register. This register holds the previous content of theProgram Counter in the "jump and save Program Counter, " jps, instruction. The Index Adder also serves as the step counter in shift, multiply, and divide. * * * * * The Control Element contains two six bit registers and severalmiscellaneous flip-flops. The latter deal with indexing, indirectaddressing, memory control, etc. The six bit registers are: Instruction Register The Instruction Register receives the first six bits of the MemoryBuffer Register during the cycle which obtains the instruction frommemory (cycle zero). This information is the primary input to theControl Element. Program Flags The six Program Flags act as convenient program switches. They are usedto indicate separate states of a program. The program can set, clear, orsense the individual flip-flops. The program can also sense or make thestate "All Flags ZERO. " They can also be used to synchronize variousinput devices which occur at random times (see Input-Output, TypewriterInput). * * * * * Three toggle switch registers are connected to the Central Processor(see Manual Controls). Test Address The fifteen Test Address Switches are used to indicate start points andto select memory registers for manual examination or change. Test Word The thirty-six Test Word Switches indicate a new number for manualdeposit into memory. They may also be used for insertion of constantswhile a program is operating by means of the operate instruction. Sense Switches The six Sense Switches allow the operator to manually select programoptions or cause a jump to another program in memory. The program cansense individual switches or the state "All Switches ZERO. " ELECTRICAL DESCRIPTION The PDP-3 circuitry is the static type using saturating transistorflip-flops and, for the most part, transistor switch elements. Theprimary active elements are Micro-Alloy and Micro-Alloy-Diffusedtransistors. The flip-flops have built-in delay so that a logic net maybe sampled and changed simultaneously. Machine timing is performed by a delay line chain. Auxiliary delay linechains time the step counter instructions (multiply, divide, etc. ). Themachine is thus internally synchronous with step counter instructionsbeing asynchronous. The machine is asynchronous for in-out operations, that is, the completion of an in-out operation initiates the followinginstruction. MECHANICAL DESCRIPTION The PDP-3 consists of two mechanical assemblies, the Console and theEquipment Frame. Fig. 3 is a photograph of PDP-1 which is an 18 bitversion of PDP-3. Console The Console is a desk approximately seven feet long. It contains thecontrols and indicators necessary for operation and maintenance of themachine. A cable connects the Console to the Equipment Frame. Equipment Frame The Equipment Frame is approximately six feet high and two feet deep. The length is a function of the amount of optional features included. The Central Processor requires a length of five and one half feet. Thepower cabinet is twenty-two inches long. A memory cabinet is thirty-twoinches long and will hold three memory modules (12, 288 words percabinet). Memory cabinets may be added at any time. Magnetic tape units require twenty-two inches per transport. A tape unitcabinet may be connected as an extension of the Equipment Frame or maybe a free-standing frame. ENVIRONMENTAL REQUIREMENTS The PDP-3 requires no special room preparation. The computer willoperate properly over the normal range of room temperature. The Central Processor and memory together require thirty amperes of 110volts single phase 60 cycle ac. Each inactive tape transport requirestwo amperes and the one active transport requires 10 amperes. CENTRAL PROCESSOR The Central Processor of PDP-3 contains the Control Element, the MemoryBuffer Register, the Arithmetic Element, and the Memory AddressingElement. The Control Element governs the complete operation of thecomputer including memory timing, instruction performance, and theinitiation of input-output commands. The Arithmetic Element, whichincludes the Accumulator, the In-Out Register, and the Carry StorageRegister, performs the arithmetic operations. The Memory AddressingElement which includes the Index Adder, the Program Counter, and theMemory Address Register, performs address bookkeeping and modification. OPERATING SPEEDS Operating times of PDP-3 instructions are normally multiples of thememory cycle of 5 microseconds. Two cycle instructions refer twice tomemory and thus require 10 microseconds for completion. Examples of thisare add, subtract, deposit, load, etc. One cycle instructions do notrefer to memory and require 5 microseconds. Examples of the latter arethe jump instructions, the skip instructions, and the operate group. Theoperating times of variable cycle instructions depend upon theinstruction. For example, the operating time for a shift or rotateinstruction is 5 +0. 2N microseconds, where N is the number of shiftsperformed. The operating times for multiply and divide are functions ofthe number of ones in the multiplier and in the quotient, respectively. Maximum time for multiply is 25 microseconds. This includes the timenecessary to get the multiply instruction from memory. Divide takes 90microseconds maximum. In-Out Transfer instructions that do not include the optional waitfunction require 5 microseconds. If the in-out device requires a waittime for completion, the operating time depends upon the device beingused. If an instruction includes reference to an index register, an additional5 microseconds is required. Each step of indirect addressing alsorequires an additional 5 microseconds. INSTRUCTION FORMAT The instructions for PDP-3 may be divided into three classes: 1. Indexable memory instructions 2. Non-indexable memory instructions 3. Non-memory instructions. The layout of the instruction word is shown in Fig. 2. The octal digits 0 and 1 define the instruction code, thus, there are 64possible instruction codes, not all of which are used. The first bit ofoctal digit 2 is the indirect address bit. If this bit is a ONE, indirect addressing occurs. The index address, X, is in octal digits 3, 4, and 5. These digitsaddress an index register for memory-type instructions. If these digitsare all ZERO, indexing will not take place. In main memory, 511 of theregisters can be used as automatic index registers. The instruction base address, Y, is in octal digits 7 through 11. Thesedigits are sufficient to address 32, 768 words of memory. Octal digit 6is reserved for further memory expansion. Space is available in theequipment frame for this expansion, should it prove desirable. In those instructions which do not refer to memory, the memory addressdigits, Y, and in some cases the index address digits also, are used tospecify the variations in any group of instructions. An example of thisis in the shift and rotate instructions in which the memory addressdigits determine the number of shifts. NUMBER SYSTEM The PDP-3 is a "fixed" point machine using binary arithmetic. Negativenumbers are represented as the 1's complement of the positive numbers. Bit 0 is the sign bit which is ZERO for positive numbers. Bits 1 to 35are magnitude bits with bit 1 being the most significant and bit 35being the least significant. The actual position of the binary point may be arbitrarily assigned tobest suit the problem in hand. Two common conventions in the placementof the binary point are: 1. The binary point is to the right of the least significant digit, thus, numbers represent integers. 2. The binary point is to the right of the sign digit, thus the numbersrepresent a fraction which lies between ±1. The conversion of decimal numbers into the binary system for use by themachine may be performed automatically by subroutines. Similarly theoutput conversion of binary numbers into decimals is done by subroutine. Operations for floating point numbers are handled by programming. Theutility program system provides for automatic insertion of the routinesrequired to perform floating point operations and number base conversion(see Utility Programs). INDEXING In PDP-3, 511 registers of the main magnetic core memory are availablefor use as automatic index registers. Their addresses are specified byoctal digits 3 to 5 of the instruction word. These registers are memorylocations 001-777 (octal). Address 000 specifies that no index registeris to be used with the instructions. The contents of octal digits 7through 11 of the selected index register are added to the unmodifiedaddress (octal digits 7 through 11 of the instruction). This sum is used to locate the operand. The addition is done in theIndex Adder which is a 15 bit 1's complement adder. The contents of theAccumulator and the In-Out Register are unaffected by the indexingprocess. An instruction which has used indexing is retained in memorywith its original address unmodified. Memory registers 1-777 (octal) areavailable for use as normal memory registers if they are not being usedas index registers. The left half of these registers is available forthe storage of constants, tables, etc. , when octal digits 7 through 11act as index registers. Three special instructions snx, spx and lir, are available to facilitateresetting, advancing, and sampling of the index registers. Since theindex registers are normal memory registers, their contents can also bemanipulated by the standard computer instructions. INDIRECT ADDRESSING An instruction which is to use an indirect address will have a ONE inbit six of the instruction word. The original address, Y, of theinstruction will not be used to locate the operand of the instruction, as is the normal case. Instead, it is used to locate a memory registerwhose contents in octal digits 7 through 11 will be used as the addressof the original instruction. This new address is known as the indirectaddress for the instruction and will be used to locate the operand. Ifthe memory register containing the indirect address also has a 1 in bitsix, the indirect addressing procedure is repeated again and a thirdaddress is located. There is no limit to the number of times thisprocess can be repeated. Index registers may be used in conjunction with indirect addressing. Inthis case, the address after being modified by the selected indexregister is used to locate the indirect address. The indirect address can be acted on by an index register and deferredagain if desired. Each use of an index register or an indirect addressextends the operating time of the original instruction by 5microseconds. INSTRUCTION LIST This list includes the title of the instruction, the normal executiontime of the instruction, i. E. , the time with no indexing and nodeferring, the mnemonic code of the instruction, and the operation codenumber. The notation used requires the following definitions. Thecontents of a register Q are indicated as C(Q). The address portion ofthe instruction is indicated by Y. The index register address of aninstruction is indicated by x. The effective address of an operand isindicated by Z. Z may be equal to Y or it may be Y as modified bydeferring or by indexing. Indexable Memory Instructions Arithmetic Instructions _Add_ (10 usec. ) add x Y Operation Code 40 The new C(AC) are the sum of C(Z) and the original C(AC). The C(Z) areunchanged. The addition is performed with 1's complement arithmetic. If the sum exceeds the capacity of the Accumulator Register, theoverflow flip-flop will be set (see Skip Group instructions). _Subtract_ (10 usec. ) sub x Y Operation Code 42 The new C(AC) are the original C(AC) minus the C(Z). The C(Z) areunchanged. The subtraction is performed using 1's complementarithmetic. If the difference exceeds the capacity of the Accumulator, the overflowflip-flop will be set (see Skip Group instructions). _Multiply_ (approximately 25 usec. ) mul x Y Operation Code 54 The C(AC) are multiplied by the C(Z). The most significant digits of theproduct are left in the Accumulator and the least significant digits inthe In-Out Register. The previous C(AC) are lost. _Divide_ (approximately 90 usec. ) div x Y Operation Code 56 The Accumulator and the In-Out Register together form a 70 bit dividend. The high order part of the dividend is in the Accumulator. The low orderpart of the dividend is in the In-Out Register. The divisor is (Z). Upon completion of the division, the quotient is in the In-Out Register. The remainder is in the Accumulator. The sign of the remainder is thesame as the sign of the dividend. If the dividend is larger than C(Z), the overflow flip-flop will be set and the division will not take place. Logical Instructions _Logical AND_ (10 usec. ) and x Y Operation Code 02 The bits of C(Z) operate on the corresponding bits of the Accumulator toform the logical AND. The result is left in the Accumulator. The C(Z)are unaffected by this instruction. Logical AND Function Table AC Bit C(Z) Bit Result 0 0 0 0 1 0 1 0 0 1 1 1 _Exclusive OR_ (10 usec. ) xor x Y Operation Code 06 The bits of C(Z) operate on the corresponding bits of the Accumulator toform the exclusive OR. The result is left in the Accumulator. The C(Z)are unaffected by this order. Exclusive OR Table AC Bit C(Z) Bit Result 0 0 0 0 1 1 1 0 1 1 1 0 _Inclusive OR_ (10 usec. ) ior x Y Operation Code 04 The bits of C(Z) operate on the corresponding bits of the Accumulator toform the inclusive OR. The result is left in the Accumulator. The C(Z)are unaffected by this order. Inclusive OR Table AC Bit C(Z) Bit Result 0 0 0 0 1 1 1 0 1 1 1 1 General Instructions _Load Accumulator_ (10 usec. ) lac x Y Operation Code 20 The C(Z) are placed in the Accumulator. The C(Z) are unchanged. Theoriginal C(Z) are lost. _Deposit Accumulator_ (10 usec. ) dac x Y Operation Code 24 The C(AC) replace the C(Z) in the memory. The C(AC) are left unchangedby this instruction. The original C(Z) are lost. _Deposit Address Part_ (10 usec. ) dap x Y Operation Code 26 Octal digits 6 through 11 of the Accumulator replace the correspondingdigits of memory register Z. C(AC) are unchanged as are the contents of octal digits 0 through 5 ofZ. The original contents of octal digits 6 through 11 of Z are lost. _Deposit Instruction Part_ (10 usec. ) dip x Y Operation Code 30 Octal digits 0 through 5 of the Accumulator replace the correspondingdigits of memory register Z. The Accumulator is unchanged as are digits6 through 11 of Z. The original contents of octal digits 0 through 5 ofZ are lost. _Load In-Out Register_ (10 usec. ) lio x Y Operation Code 22 The C(Z) are placed in the In-Out Register. C(Z) are unchanged. Theoriginal C(IO) are lost. _Deposit In-Out Register_ (10 usec. ) dio x Y Operation Code 32 The C(IO) replace the C(Z) in memory. The C(IO) are unaffected by thisinstruction. The original C(Z) are lost. _Jump_ (5 usec. ) jmp x Y Operation Code 60 The Program Counter is reset to address Z. The next instruction thatwill be executed will be taken from memory register Z. The originalcontents of the Program Counter are lost. _Jump and Save Program Counter_ (5 usec. ) jsp x Y Operation Code 62 The contents of the Program Counter are transferred to the Index Adder. When the transfer takes place, the Program Counter holds the address ofthe instruction following the jsp. The Program Counter is then reset toaddress Z. The next instruction that will be executed will be taken frommemory register Z. _Skip if Accumulator and Z differ_ (10 usec. ) sad x Y Operation Code 50 The C(Z) are compared with the C(AC). If the two numbers are different, the Program Counter is indexed one extra position and the nextinstruction in the sequence is skipped. The C(AC) and the C(Z) areunaffected by this operation. _Skip if Accumulator and Z are the same_ (10 usec. ) sas x Y Operation Code 52 The C(Z) are compared with C(AC). If the two numbers are identical, theProgram Counter is indexed one extra position and the next instructionin the sequence is skipped. The C(AC) and C(Z) are unaffected by thisoperation. Non-Indexable Memory Instructions These instructions have the same word format as the indexableinstructions. Since they operate on the index register location, x, theycannot be indexed. _Skip on Negative index_ (10 usec. ) snx x Y Operation Code 46 The number in octal digits 7 through 11 of the instruction word is addedto the C(x). This addition is done in the 15 bit Index Adder using 1'scomplement arithmetic. If, after the addition, the sum is negative, theProgram Counter is advanced one extra position and the next instructionin the sequence is skipped. The contents of octal digits 0-5 of theindex register location are unaffected by this instruction. _Skip on Positive index_ (10 usec. ) spx x Y Operation Code 44 The number in octal digits 7 through 11 of the instruction word is addedto the C(x). This addition is done in the 15 bit Index Adder using 1'scomplement arithmetic. If, after the addition, the sum is positive, the Program Counter isadvanced one extra position and the next instruction in the sequence isskipped. The contents of octal digits 0-5 of the index register locationare unaffected by this instruction. _Load Index Register_ (10 usec. ) lir x Y Operation Code 14 The octal digits 7 through 11 (Y) of the instruction will replace thecorresponding digits of the memory register specified by x. Octal digit6 of the memory register will be left clear. Digits 0-5 of the memoryregister are unchanged. _Deposit Index Adder_ (10 usec. ) dia x Y Operation Code 16 The C(IA) replace the octal digits 7 through 11 of memory location Y. Octal digit 6 of Y is cleared. Digits 0 through 5 of Y are leftunchanged. The x portion of the instruction is ignored. Non-Memory Instructions Rotate and Shift Group This group of instructions will rotate or shift the Accumulator and/orthe In-Out Register. When the two registers operate combined, the In-OutRegister is considered to be a 36 bit magnitude extension of the rightend of the Accumulator. Rotate is a non-arithmetic cyclic shift. That is, the two ends of theregister are logically tied together and information is rotated asthough the register were a ring. Shift is an arithmetic operation and is in effect multiplication of thenumber in the register by 2^{+N}, where N is the number of shifts. Shiftor rotate instructions involving more than 33 steps can be used forsimulating time delays. 36 rotate steps of the Accumulator will returnall information to its original position. _Rotate Accumulator Right_ (13 usec. Maximum for 36 shifts) rar N Operation Code 671 This instruction will rotate the bits of the Accumulator right Npositions, where N is octal digits 7-11 of the instructions word. _Rotate Accumulator Left_ (13 usec. Maximum for 36 shifts) ral N Operation Code 661 This instruction will rotate the bits of the Accumulator left NPositions, where N is octal digits 7-11 of the instruction word. _Shift Accumulator Right_ (13 usec. Maximum for 36 shifts) sar N Operation Code 675 This instruction will shift the contents of the Accumulator right Npositions, where N is octal digits 7-11 of the instruction word. _Shift Accumulator Left_ (13 usec. Maximum for 36 shifts) sal N Operation Code 665 This instruction will shift the contents of the Accumulator left Npositions, where N is octal digits 7-11 of the instruction word. _Rotate In-Out Register Right_ (13 usec. Maximum for 36 shifts) rir N Operation Code 672 This instruction will rotate the bits of the In-Out Register right Npositions, where N is octal digits 7-11 of the instruction word. _Rotate In-Out Register Left_ (13 usec. Maximum for 36 shifts) ril N Operation Code 662 This instruction will rotate the bits of the In-Out Register left Npositions, where N is octal digits 7-11 of the instruction word. _Shift In-Out Register Right_ (13 usec. Maximum for 36 shifts) sir N Operation Code 676 This instruction will shift the contents of the In-Out Register right Npositions, where N is octal digits 7-11 of the instruction word. _Shift In-Out Register Left_ (13 usec. Maximum for 36 shifts) sil N Operation Code 666 This instruction will shift the contents of the In-Out Register left Npositions, where N is octal digits 7-11 of the instruction word. _Rotate AC and IO Right_ (13 usec. Maximum for 36 shifts) rcr N Operation Code 673 This instruction will rotate the bits of the combined register right ina single ring N positions, where N is octal digits 7-11 of theinstruction word. _Rotate AC and IO Left_ (13 usec. Maximum for 36 shifts) rcl N Operation Code 663 This instruction will rotate the bits of the combined register left in asingle ring N position, where N is octal digits 7-11 of the instructionword. _Shift AC and IO Right_ (13 usec. Maximum for 36 shifts) scr N Operation Code 677 This instruction will shift the contents of the combined register rightN positions, where N is octal digits 7-11 of the instruction word. _Shift AC and IO Left_ (13 usec. Maximum for 36 shifts) scl N Operation Code 667 This instruction will shift the contents of the combined registers leftN positions, where N is octal digits 7-11 of the instruction word. * * * * * _Skip Group_ (5 usec. ) skp Y Operation Code 64 This group of instructions senses the state of various flip-flops andswitches in the machine. It does not require any reference to memory. The address portion of the instruction selects the particular functionto be sensed. All members of this group have the same operation code. _Skip on ZERO Accumulator_ (5 usec. ) sza Address 100 If the Accumulator is equal to plus ZERO (all bits are ZERO) the ProgramCounter is advanced one extra position and the next instruction in thesequence is skipped. _Skip on Plus Accumulator_ (5 usec. ) spa Address 200 If the sign bit of the Accumulator is ZERO, the Program Counter isadvanced one extra position and the next instruction in the sequence isskipped. _Skip on Minus Accumulator_ (5 usec. ) sma Address 400 If the sign bit of the Accumulator is ONE, the Program Counter isadvanced one extra position and the next instruction in the sequence isskipped. _Skip on ZERO Overflow_ (5 usec. ) szo Address 1000 If the overflow flip-flop is a ZERO the Program Counter is advanced oneextra position and the next instruction in the sequence will be skipped. The overflow flip-flop is cleared by this instruction. This flip-flop isset by addition, subtraction, or division that exceeds the capacity ofthe Accumulator. The overflow flip-flop is not cleared by arithmeticoperations which do not cause an overflow. Thus, a whole series ofarithmetic operations may be checked for correctness by a single szo. The overflow flip-flop is cleared by the "Start" Switch. _Skip on Plus In-Out Register_ (5 usec. ) spi Address 2000 If the sign digit of the In-Out Register is ZERO the Program Counter isindexed one extra position and the next instruction in the sequence isskipped. _Skip on ZERO Switch_ (5 usec. ) szs Addresses 10, 20, . . . 70 If the selected Sense Switch is ZERO, the Program Counter is advancedone extra position and the next instruction in the sequence will beskipped. Address 10 senses the position of Sense Switch 1, Address 20Switch 2, etc. Address 70 senses all the switches. If 70 is selected all6 switches must be ZERO to cause the skip to occur. _Skip on ZERO Program Flag_ (5 usec. ) szf Addresses 0 to 7 inclusive If the selected program flag is a ZERO, the Program Counter is advancedone extra position and the next instruction in the sequence will beskipped. Address 0 is no selection. Address 1 selects program flag one, etc. Address 7 selects all programs flags. All flags must be ZERO tocause the skip. The instructions in the One Cycle Skip group may be combined to form theinclusive OR of the separate skips. Thus, if address 3000 is selected, the skip would occur if the overflow flip-flop equals ZERO or if theIn-Out Register is positive. The combined instruction would still take 5microseconds. * * * * * _Operate Group_ (5 usec. ) opr Y Operation Code 76 This instruction group performs miscellaneous operations on variousCentral Processor Registers. The address portion of the instructionspecifies the action to be performed. _Clear In-Out Register_ (5 usec. ) cli Address equal 4000 This instruction clears the In-Out Register. _Load Accumulator from Test Word_ (5 usec. ) lat Address 2000 This instruction forms the inclusive OR of the C(AC) and the contents ofthe Test Word. This instruction is usually combined with address 200(clear Accumulator), so that C(AC) will equal the contents of the TestWord Switches. _Complement Accumulator_ (5 usec. ) cma Address 1000 This instruction complements (makes negative) the contents of theAccumulator. _Halt_ hlt Address 400 This instruction stops the computer. _Clear Accumulator_ (5 usec. ) cla Address 200 This instruction clears (sets equal to plus 0) the contents of theAccumulator. _Clear Selected Program Flag_ (5 usec. ) clf Address 01 to 07 inclusive The selected program flag will be cleared. Address 00 selects no programflag, 01 clears program flag 1, 02 clears program flag 2, etc. Address07 clears all program flags. _Set Selected Program Flag_ (5 usec. ) stf Address 11 to 17 inclusive * * * * * _In-Out Transfer Group_ (5 usec. Without in-out wait) iot x Y Operation Code 72 The variations within this group of instructions perform all the in-outcontrol and information transfer functions. If bit six (normally theIndirect Address bit) is a ONE, the computer will halt and wait for thecompletion pulse from the device activated. When this device deliversits completion, the computer will resume operation of the instructionsequence. An incidental fact which may be of importance in certain scientific orreal time control applications is that the time origin of operationsfollowing an in-out completion pulse is identical with the time of thatpulse. Most in-out operations require a known minimum time before completion. This time may be utilized for programming. The appropriate In-OutTransfer is given with no in-out wait (bit six a ZERO). The instructionsequence then continues. This sequence must include an iot instructionwhich performs nothing but the in-out wait. This last instruction mustoccur before the safe minimum time. A table of minimum times for allin-out devices is delivered with the computer. It lists minimum timebefore completion pulse and minimum In-Out Register free time. The details of the In-Out Transfer variations are listed underInput-Output. The mnemonic codes and addresses for the standard equipment are: _Read Paper Tape Alphanumeric Mode_ rpa Address 1 _Read Paper Tape Binary Mode_ rpb Address 2 _Typewriter Output_ tyo Address 3 _Typewriter Input_ tyi Address 4 _Punch Paper Tape Alphanumeric Mode_ ppa Address 5 _Punch Paper Tape Binary Mode_ ppb Address 6 MANUAL CONTROLS The Console of PDP-3 has controls and indicators for the use of theoperator. Fig. 4 is a close-up of the control panel of PDP-1, the 18 bitversion of PDP-3. All computer flip-flops have indicator lights on theConsole. These indicators are primarily for use when the machine hasstopped or when the machine is being operated one step at a time. Whilethe machine is running, the brightness of an indicator bears somerelationship to the relative duty factor of that particular flip-flop. Three registers of toggle switches are available on the Console. Theseare the Test Address (15 bits), the Test Word (36 bits), and the SenseSwitches (6 bits). The first two are used in conjunction with theoperating push buttons. The Sense Switches are present for manualintervention. The use of these switches is determined by the program(see System Block Diagram and Skip Group Instructions). Operating Push Buttons _Start_ - When this switch is operated, the computer will start. Thefirst instruction comes from the memory location indicated in the TestAddress Switches. _Stop_ - The computer will come to a halt at the completion of thecurrent memory cycle. _Continue_ - The computer will resume operation starting at the stateindicated by the lights. _Examine_ - The contents of the memory register indicated in the TestAddress will be displayed in the Accumulator and the Memory Bufferlights. _Deposit_ - The word selected by the Test Word Switches will be put inthe memory location indicated by the Test Address Switches. _Read-In_ - When this switch is operated, the photoelectric paper tapereader will start operating in the Read-In mode. (see Input-Output). In addition to the operating push buttons, there are several separatetoggle switches. _Single Cycle Switch_ - When the Single Cycle Switch is on, the computerwill halt at the completion of each memory cycle. This switch isparticularly useful in debugging programs. Repeated operation of theContinue Switch button will step the program one cycle at a time. Theprogrammer is thus able to examine the machine states at each step. _Test Switch_ - When the Test Switch is on, the computer will performthe instruction indicated in the Test Address location. It will repeatthis instruction either at the normal speed rate or at a single cyclerate if the Single Cycle Switch is up. This switch is primarily usefulfor maintenance purposes. _Sense Switches_ - There are six switches on the Console which arepresent for manual intervention. STORAGE The internal Memory System for PDP-3 consists of modules of 4096 wordsof coincident current magnetic core storage. Each word has 36 bits. Thememory modules operate with a read-rewrite cycle time of 5 microseconds. The driving currents of the memory are automatically adjusted tocompensate for normal room temperature variations. Each core memory module consists of the memory stack, the required X andY switches, the X and Y current sources and sense amplifiers for thatstack. The Memory Address Register, the Memory Buffer Register, and the MemoryTiming Controls are considered to be part of the Central Processor. Thestandard PDP-3 Memory Address Register configuration is built to allowup to 8 modules of core memory (32, 768 words). There is a space in theaddressing section of the machine to allow expansion of the addressingby a factor of eight for a total addressing capacity of 262, 144 memoryregisters. The Core Memory may be supplemented by Magnetic Tape Storage. This isdescribed under Input-Output. STANDARD INPUT-OUTPUT The PDP-3 is designed to accommodate a variety of input-outputequipment. Standard input-output units include a Paper Tape Reader, Paper Tape Punch and an Electric Typewriter. A single instruction, In-Out Transfer (see Central Processor), performsall in-out operations through the 36 bit In-Out Register. The addressportion of this instruction specifies the in-out function. One bit ofthe instruction selects an in-out halt as required. PAPER TAPE READER The Paper Tape Reader of the PDP-3 is a photoelectric device capable ofreading 300 lines per second. Six lines form the standard 36 bit wordwhen reading binary punched eight hole tape. Five, six and seven holetape may also be read. The reader will operate in one of two basic modes or in a third specialmode. Alphanumeric Mode rpa iot 1 In this mode, one line of tape is read for each In-Out Transfer. Alleight holes of the line are read. The information is left in the righteight bits of the In-Out Register, the remainder of the register beingleft clear. The standard PDP alphanumeric paper tape code includes anodd parity bit which may be checked by the program. Tape of non-standardwidth would be read in this mode. Binary Mode rpb iot 2 For each In-Out Transfer instruction, six lines of paper tape are readand assembled in the In-Out Register to form a full computer word. For aline to be recognized in this mode, the eighth hole must be punched;i. E. , lines with no eighth hole will be skipped over. The seventh holeis ignored. The pattern of holes in the binary tape is arranged so as tobe easily interpreted visually in terms of machine instruction. Read-In Mode This is a special mode activated by the "Read-In" Switch on the Console. It provides a means of entering programs which neither rely on read-inprograms in memory nor require a plug board. Pushing the "Read-In"Switch starts the reader in the binary mode. The first group of sixlines and alternate succeeding groups of six lines are interpreted as"Read-In" mode instructions. Even-numbered groups of 6 lines are data. The "Read-In" mode instructions must be either "deposit in-out" (dio Y)or "jump" (jmp Y). If the instruction is dio Y, the next group of sixbinary lines will be stored in memory location Y and the readercontinues moving. If the instruction is jmp Y, the "Read-In" mode isterminated and the computer will commence operation at the address ofthe jump instruction. PAPER TAPE PUNCH The standard PDP-3 Paper Tape Punch has a nominal speed of 20 lines persecond. It can operate in either the alphanumeric mode or the binarymode. Alphanumeric Mode ppa iot 5 For each In-Out Transfer instruction one line of tape is punched. In-OutRegister bit 35 conditions hole #1. Bit 34 conditions hole #2, etc. Bit28 conditions hole #8. Binary Mode ppb iot 6 For each In-Out Transfer instruction one line of tape is punched. In-OutRegister bit five conditions hole #1. Bit four conditions hole #2, etc. Bit zero conditions hole #6. Hole #7 is left blank. The #8 hole isalways punched in this mode. TYPEWRITER The Typewriter will operate in the input mode or the output mode. Output Mode tyo iot 3 For each In-Out Transfer instruction one character is typed. Thecharacter is specified by the right six bits of the In-Out Register. Input Mode tyi iot 4 This operation is completely asynchronous and is therefore handleddifferently than any of the preceding in-out operations. When a Typewriter key is struck, Program Flag Number One is set. At thesame time the code for the struck key is presented to gates connected tothe right six bits of the In-Out Register. This information will remainat the gate for a relatively long time by virtue of the slow mechanicalaction. A program designed to accept typed-in data would periodicallycheck the status of Program Flag One. If at any time Program Flag One isfound to be set, an In-Out Transfer instruction with address four mustbe executed for information to be transferred. This In-Out Transfernormally should not use the optional in-out halt. The informationcontained in the Typewriter's coder is then read into the right six bitsof the In-Out Register. OPTIONAL INPUT-OUTPUT The PDP-3 is designed to accommodate a variety of input-outputequipment. Of particular interest is the ease with which new, andperhaps unusual, external equipment can be added to the machine. Optional in-out devices include Cathode Ray Tube Display, Magnetic Tape, Real Time Clock, Line Printer and Analog to Digital Converters. Themethod of operation of PDP-3 with these optional devices is similar tothe standard input-output equipment. SEQUENCE BREAK SYSTEM An optional in-out control is available for PDP-3. This control, termedthe Sequence Break System, allows concurrent operation of several in-outdevices and the main sequence. The system has, nominally, 16 automaticinterrupt channels arranged in a priority chain. A break to a particular sequence may be initiated by the completion ofan in-out device, the program, or an external signal. If this sequencehas priority, the C(AC), C(IO), C(PC), and C(IA) are stored in threefixed memory locations unique to that sequence. Since the C(PC) andC(IA) are eighteen bits each, these two registers are stored in onememory location. The next instruction is taken from a fourth location. This instruction is usually a jump to a suitable routine. The program isnow operating in the new sequence. This new sequence may be broken by ahigher priority sequence. A typical program loop for handling an in-outsequence would contain 3 to 5 instructions, including the appropriateiot. These are followed by load AD and load IO from the fixed locationsand a special indirect jump through the location of the previous C(PC). This special jump also loads the IA. This last instruction terminatesthe sequence. HIGH SPEED IN-OUT CHANNEL The device connected to an in-out channel communicates directly withmemory through the Memory Buffer Register. At the completion of eachmachine instruction, a check is made to see if the in-out channel has aword for, or needs a word from, the memory. When necessary, a memorycycle is taken to serve the channel. The operation is initiated by anin-out command. The in-out transfer command indicates the nature of thetransfer. The left half of the In-Out Register must contain thestarting address of the transfer, and the right half must contain thenumber of words to be transferred. If the Sequence Break System isconnected, the completion of the transfer will signal the propersequence. If no Sequence Break System is connected, the completion ofthe in-out channel transfer sets a program flag. MAGNETIC TAPE The system consists of tape units connected to the PDP-3 through a tapecontrol (TC). This tape is read or written in IBM 729I format. Twohundred characters, each having 6 bits plus a parity bit, are written oneach inch of tape and the tape moves at 75 inches/sec. The tape controlhas the job of connecting a specific unit to the PDP-3 and is a switch. It also has the function of controlling the format of information thatis read or written on tape. In-out class commands instruct TC to thetype of information transfer and select the tape unit. Another IOTcommand synchronizes the transfer of information through the TC to thecomputer. The IOT order to select the unit and function is decoded as follows: 1)Three bits specify the function of TC. 2) The remaining 6 bits selectthe unit. _IOT Motion Commands for Magnetic Tape Units_ _IOT Code_ _Abbreviation_ _Function_ 73. . . . Nn 60 mrb Read a binary record. 73. . . . Nn 61 mra Read an alphanumeric (BCD) record. 73. . . . Nn 62 mbb Backspace a binary record. 73. . . . Nn 63 mba Backspace an alphanumeric record. 73. . . . Nn 64 mwb Write a binary record. 73. . . . Nn 65 mwa Write an alphanumeric record. 73. . . . Nn 66 mlp Move tape to lead point (rewind). Where the octal digits, nn, specify the unit number. The motion commands have the deferred bit, thus, the program halts. Ifthe TC is free, the command will be transferred to the tape control foraction and the program restarts immediately. If the tape control iscurrently busy with an instruction, i. E. , it hasn't finished a previouscommand, the motion command is held up until TC is free to execute thenew command. The transfer of information from the computer to the TC is accomplishedwith the pause and skip command, MPS or IOT 70. This command has thedeferred bit and halts a program until the TC can handle the transfer. On completion, the transfer occurs and the program restarts. This isused exclusively to synchronize the flow of information between a tapeunit and the computer. This command normally skips the followinginstruction. If a flag is set in the TC, indicating incorrectinformation flow, the skip does not take place. The TC contains a 36 bit buffer which holds a complete word whileinformation is read or written. When an MPS order is given and the unitis reading, the TC buffer is read into the IO. The MPS order givenduring writing causes the IO to be transferred to the TC buffer. Various conditions occurring in the TC cause the no-skip condition, whenan MPS is given. Tape control flags are examined by the command, examineand clear flags, MEC or IOT 71. When MEC is given, the flags are putinto the IO for program interrogation, and the flags cleared. The flagsare: parity, end of tape, an end of record flag, and reading-writingcheck. The parity flag is set if the parity condition is not met while the tapeis being read (during MWA, MWB, MRA, or MRB). The end of tape flag is set when the tape comes to the end of tape, moving in either direction. Three conditions set the read-write check flag: 1) If TC is inactive, i. E. , no unit or function selected, and an MPS instruction is given. TheMPS becomes a no-operation, no-halt instruction. 2) When readinginformation and not emptying the TC buffer, by giving an MPS before moreinformation arrives from tape. 3) A unit becomes unavailable during anormal sequence. The end of record flag is set during reading or backspacing when thetape comes to an end of record gap. _Writing a Record of Information_ Information is written on the tape by giving a MWB or MWA command. Thissets a write binary or a write alphanumeric into the TC and selects theunit. A motion select command is executed immediately if the TC is free, otherwise, the command waits until it can be executed. Normalprogramming can continue after the MWA or MWB is given for approximately5 milliseconds. At this time, an MPS order is given and the programpauses until information can be written. When the MPS is restarted, information is transferred to the TC buffer from the IO. If no flagshave been set, the following instruction is skipped. Three-quarter inches of blank tape is written by giving either the MWAor MWB order. An end of file is written as follows: 1) Four MWA commandswrite three inches of blank tape. 2) Then end of file character iswritten by giving the MPS order. Information is read and checked for correct parity while writing. If too many program steps are given between the motion select command, MWA or MWB and the first MPS, the unit will deselect (or disconnect). The MPS is then a no-operation command. _Writing Program_ As an example, a program to write k words in binary format from storagebeginning in register A, using tape unit number 04, is shown. Thefollowing program is written in standard FRAP language. The programbegins in register enterwrite. enterwrite mec, clear flags initially mwb 400, 73000000464 lir x/-k+1, initialize index register x b lio x/a+k-1, begin loop mps, wait for TC then write C(Z) jmp c, error spx x/1, add 1 to index register x jmp b, return of loop jmp done, record written c mec, tape error ril 1 spi jmp rwcstop, read-write error or tape fault ril 1 spi jmp b+3, tape end hlt, tape parity done, resume programming _Reading Information_ Information is read by giving the MRA or MRB order. Almost 10 ms. Isavailable after a read order is given before information actually entersthe TC buffer. To read a record of unknown length, the read order is first given. TheMPS order halts the program until six characters are assembled in the TCinformation buffer. The next instruction after the MPS, a jumpinstruction, transfers control from the loop when any flag is set. Thenext instruction deposits the IO. The record length is determined by notskipping after the MPS order on the setting of the end of record flag. The read-write check flag or the end of record flag is then interrogatedto see that the tape is actually at the end of record. If a tape is notat the end of record, then the tape is either at the end of the reel, ora parity check has occurred. _Reading Program_ Program to read j binary words into storage beginning in register d, using tape unit 10, j is unknown. The program begins in registerenteread. enteread mec, clear flags initially mrb 1000, 730000001060 dzm x, put zero in memory location x e mps jmp outcheck dio x/d, store in location modified by x snx x/+1, add 1 to C(x) jmp e outcheck mec, examine flags spi, end of record? jmp recordend, yes hlt, error recordend snx x/+1, to find value of j ", resume programming C(IA) = j " " " _Forward Spacing_ Forward spacing is done by giving an MRB or MRA order. This moves thetape forward with the read-write head positioned at the end of thefollowing record. If n read orders are given, the tape is spaced forwardn records. By giving the MEC order, parity flags are examined to seethat information on tape has been read correctly. _Backspacing_ By giving an MBA or MBB order the tape is moved backwards a record withthe read-write heads positioned in the previous end of record gap. Theend of record flag is set when the tape has moved backwards a record. _Rewinding_ Rewinding is accomplished by giving the rewind order, move tape to loadpoint, MLP. The rewind order starts a unit rewinding and does not tie upthe TC. If a motion command is given which calls for a unit that isrewinding, the command is executed, but the action will not take placeuntil the unit is available. _Unit Availability_ A unit is unavailable to the program under the following conditions: 1. Unit is rewinding. 2. Tape is improperly loaded. 3. Cover door open. 4. Unit overloaded. 5. Unit under manual control. 6. Power off. A selected but unavailable unit holds up the TC if a motion order isgiven for the unit. The TC will be held up until the unit is ready. _Flag Positions_ _IO Bit_ _Flag_ 0 EOR - End of record 1 RWF - Read-Write 2 EOT - End of Tape 3 Parity _Connection with High Speed Channel_ The high speed channel directs the tape control, and word transfer, justas a program would. A unit is first started reading or writing. The highspeed channel is given the memory location of the information, and thenumber of registers the words read or written will occupy. The channeleffects the information transfer. Thus, a high speed channel connectedto a tape control handles the programming for the unit word transfers. Completion of the block transfer is signified by either setting aprogram flag, or entering the sequence break. _Connection with Sequence Break System_ When the TC is connected to the Sequence Break System, the program isautomatically interrupted each time an MPS command needs to be given. Programming is unaffected during reading and a record may be read withno flags set. The TC initiates breaks so that an MPS may be given intime. Similarly, the break is initiated during writing each time an MPS needsto be given. _Motion Command Summary_ _Time before _Time between _Time after End of _Flags that first MPS_ MPS's_ Record to deselect_ may be set_ MWA 3 ms. 400 us. 10 ms. RWF (if unit MWB (longer time is deselected causes deselection) and MPS given, or unit becomes unavailable), Parity, EOT. MRA 7 ms. < 400 us. 5 ms. RWF, (if MRB (longer time information misses information, is missed, or and unit becomes rwc set) unavailable), EOT, EOR, Parity. MBA - - 10 ms. RWF (if unit MBB becomes unavailable), EOR, EOT. CATHODE-RAY-TUBE DISPLAY The PDP-3 Cathode Ray Tube Display is useful for presentation ofgraphical or tabular information to the operator. It uses a 16 inchround tube with magnetic deflection. For each In-Out transfer order, onepoint is displayed at the position indicated by the In-Out Register. Bits 0-9 of the IO indicate the X coordinate of the position, and bits18-27 indicate the Y coordinate. The display takes 60 microseconds. An additional display option is a Light Pen. By use of this device thecomputer is signaled that the operator is interested in the last pointdisplayed. Thus the program can take appropriate action such as changingthe display or shifting operation to another program. A smaller display is available. This display uses a five inch, highresolution cathode ray tube. The tube is equipped with a mounting bezelto accept a camera or photomultiplier device. The operation of thisdisplay is similar to that of the 16 inch, except that 12 bits aredecoded for each axis. REAL TIME CLOCK A special input register may be connected to operate as a Real TimeClock. This is a counting register operated by a crystal controlledoscillator. The clock can be reset to zero by manual operation. A toggleswitch interlock prevents an accidental reset. The state of this countermay be read at any time by the appropriate In-Out Transfer instruction. LINE PRINTER A 72 column Anelex printer and control are available as an option forPDP-3. The control contains a one line buffer. This buffer is cleared bythe completion of an order to space the paper one position (psp). Thebuffer is filled from the In-Out Register by a succession of 12 loadbuffer orders (plb). The first plb will put the six charactersrepresented by C(IO) in the leading (left-hand) column positions of thebuffer. After the buffer is loaded, the order, print (pnt), is given. UTILITY PROGRAMS FRAP-3 - The Assembly Program An assembler or compiler prepares a machine language tape suitable fordirect interpretation by the computer from a program tape in operatorlanguage. Generally speaking, one statement accepted by FRAP producesone instruction for the machine. A single statement written for thePDP-3 compiler, DECAL-3, may cause several instructions to be written. Thus, FRAP causes a 1 for 1 mapping of instructions for statements whileDECAL may produce many instructions from one statement. In addition to allowing program tapes to be prepared with off lineequipment, an assembly program has other functions. Normally, themachine would require 36 bits or 12 octal digits to be written for eachinstruction used in the machine. FRAP allows mnemonic symbols to be usedfor the instructions. These mnemonic symbols aid the programmer byrepresenting the instruction in an easily remembered form. In addition to allowing mnemonic symbols to represent the instructions, variable length sequences of alphanumeric characters may be used torepresent memory addresses in symbolic form. The assembly program doesthe address bookkeeping for the programmer. A short example of a FRAPprogram is on Page 29. Since few characters limit or control the format of instructions writtenin FRAP-3 language, it is possible to write instructions in almost anyformat or style. FRAP-3 may also be used to prepare tapes for interpretive programming, since arbitrary definitions for operation code symbols are permitted. A feature useful both for ease of programming and for machine simulationis the ability to call for a series of instructions (macro-instruction)to be written. Frequently used instruction sequences thus need only tobe defined once. DECAL - The Compiler Program DECAL-3 (Digital Equipment Compiler, Assembler, and Linking loader forPDP-3) is an integrated programming system for PDP-3. It incorporates inone system all of the essential features of advanced assemblers, compilers, and loaders. DECAL is both an assembler and compiler. It combines the one-to-onetranslation facilities of an assembler, and the one-to-many translationfacilities of a formula translation compiler. Problem oriented languagestatements may be freely intermixed with symbolic machine languageinstructions. A flexible loader is available to allow the specificationof program location at load time. The programmer may specify thatcertain variables and constants are "systems" variables and constants. The symbols so defined are universally used in a system of manyroutines. Thus, communications between parts of a major program isfacilitated even though these parts may be compiled separately. Storagerequirements for a large program are lessened by this technique. DECAL is an open-ended programming system and can be modified without adetailed understanding of the internal operation. This is achieved bymeans of a recursive definition facility based on a skeleton compilerwith a small set of logical capabilities. The skeleton compiler acts asa bootstrap for introducing more sophisticated facilities. The compiler will be delivered with a fully defined subset of formulatranslation operators. Additional subsets may be defined by the user tobest fit his source language. FLOATING POINT SUBROUTINES A set of subroutines are provided with the PDP-3 to perform floatingpoint arithmetic. In these, the PDP-3 36 bit word is divided to form a27 bit mantissa, a, and 9 bit exponent, b. Numbers, thus, appear in theform: k = ax2^b where, a, is considered to be in fractional form in therange 1/2